Model Number |
T.A.S ( Total ASIC Service ) |
Features
C&S Technology's ASIC Design Service is dedicated to the best customer service for the purpose of successfully offering Total ASIC Service. ASIC Design Service provided by C&S Technology is classified roughly into Level-0 / Level-1 / Level-2 services. In addition, it offers other main services like Design Kit Set-Up / Foundry Interface / EDA Tool support / CTS / STA / DFT / Design Consulting(X-talk, power consumption) / Customer Room operation. It also holds various types of Sample / Mass Production Service to offer Mask Revision / defect analysis / mass-production Set-Up / mass-production support / various Sample Service / marketing. C&S Technology secures the best-qualified Back-End Layout Engineers with more than 10 years of experiences, so that it may meet the customer needs through the best optimized and stabilized physical design.
ASIC Design Service
- Level-0
We develop ASIC in accordance with specifications you want only. (if customers give a request for design, we carry out Full Chip or partial design accordingly, and develop ASIC through a whole process ranged from HDL design to Back-End Layout & PG process.)
- Level-1
We develop the HDL-designed circuit with ASIC. (If customers give a request for HDL-designed circuit like the FPGA-proven circuit, we develop ASIC by carrying our whole process ranged from design/verification stage to Back-End Layout & PG process in accordance with the Foundary company`s Library.)
- Level-2
We develop ASIC by using the circuit designed for the Foundry company's Library. (If customers give a request on DB suitable for Foundry company's Library, we develop ASIC by carrying from synthesis to PG process and Customer Sample delivery.)
- Other main services
- Design Kit Set-Up & Fab-Vender Interface service (It supports the interface with Fab-Vendor for smooth design process and offers Samsung's Sign-off Flow & Manual.)
- Necessary EDA Tool support service (Customer Design Room)
- Special Cell support service
- CTS(Clock Tree Synthesis) service
- STA(Static Timing Analysis) service
- DFT(Design For Testability) service
- Design Consulting service (Offering design know-how (aliveblock, power consumption, cross-talk) upon designing Architecture & Front-end.)
- Customer Design Room operation service (Offering the environment where customers can design for themselves.)
Sample, Mass Production Service
- Main services
- Mask Revision service
- Defect analysis service (Offering prompt and correct service on defect analysis)
3) Mass-production Set-Up & support service (Carrying out mass-production Set-Up, quantity, due date & better price competitiveness as proxy)
- Various types of sample services (Offering various packages, bare chip services.)
- Marketing service (Offering sample delivery, marketing services)
ASIC Design Flow
C&S Technology shares Samsung Electronics' ASIC Design Flow, and also shares Samsung Electronics' Design Methodology. And it does its best to maintain the maximum design reliability / Hit Ratio / yield.
ISO 9001 acquisition
C&S Technology carries out quality control activities under the management objectives of 'Brand-name management'for 'Best technology'and 'Best quality'. And it puts all efforts into customer satisfaction, for example, by acquiring ISO 9001 in 2000.
Compiled Macrocells Overview
Design Procedure |
EDA Tool |
Schematic Base |
Cadence Virtuoso |
Logic Simulation |
Cadence Verilog-XL, Cadence NC-Verilog, Synopsys VCS |
Logic Synthesis |
Synopsys Design Compiler |
DFT, Scan Insertion & ATPG |
Synopsys Test Compiler, Synopsys TetraMax |
Static Timing Analysis |
Synopsys PrimeTime |
Floor Planner |
Avant! PlanetPL |
Place & Route |
Synopsys Astro, Avant! Apollo |
Delay Calculation |
SEC CubicDelay |
RC Analysis |
Avant! Star-RCXT |
Power Analysis |
SEC CubicPower, Davan! Power Theater |
Fault Simulation |
SEC SuperTest |
DRC/LVS |
Cadence Dracula, Mentor Calibre |
PG |
SEC In-house Tool |
Package Overview
Supports various packages like QFP, thin QFP, low profile QFP, power QFP, BGA,
plastic BGA, super BGA and plastic leaded chip carrier.
Accumulated experiences & know-how on ASIC design
It supports successful projects based
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